Quartus prime
EECE 343 Activity 2 Fall 2020
Activity 2
Condition Code Checker
Prof. Kredo
Due: 23:59 September 4
In this activity you will accomplish several goals:
Develop a combinational block in Verilog using dataflow modeling Run a simulation to verify correct operation
Work individually for this activity using your computer.
Prelab
Ensure you have Quartus Prime Lite installed and that you are able to program your board as required in Activity 1.
Derive the Boolean equation for the satisfied output described in Table 1. You may minimize the equations, but this is not required.
Introduction
Your goal for this activity is to implement a condition code checker, which evaluates a processors condition flags based on a selected condition and determines if the condition is satisfied. A condition code checker might be used in a processor to determine whether or not to take a conditional branch. For example, if the processor executes BEQ (branch on equal), the condition code checker determines if the previous operation resulted in an equal condition.
The condition code checker you will build has these inputs
code the 4-bit condition to check Z,N,C,V four 1-bit values indicating the processor flags (Z)ero, (N)egative, (C)arry, and o(V)erflow
and this output
satisfied a 1-bit value which is high (1) when the condition is met and low (0) otherwise
Table 1 lists the conditions you have to implement for this assignment. For example, if the code equals 0011 and the C input is low, then the condition code checker should output a high value. If the code equals 0101 and the N input is high, then the condition code checker should output a low value.
EECE 343 Activity 2 Fall 2020
Condition Name code NZCV satisfied
Equal 0000 X0XX 0
X1XX 1
Not Equal 0001 X0XX 1
X1XX 0
Carry Set 0010 XX0X 0
XX1X 1
Carry Clear 0011 XX0X 1
XX1X 0
Minus 0100 0XXX 0
1XXX 1
Plus 0101 0XXX 1
1XXX 0
Overflow Set 0110 XXX0 0
XXX1 1
Overflow Clear 0111 XXX0 1
XXX1 0
Unused 1XXX XXXX X
Table 1: Condition Code Checker Truth Table
Implementation
You are to implement the condition code checker in SystemVerilog as combinational logic using dataflow modeling. That means you may only use:
assign statements primitives
A module definition and testbench have been provided in the activity2.qar file available on Blackboard Learn. Implement your module and verify that it works correctly by running an RTL simulation using the testbench provided in your project. Correct any errors until you pass the simulation.
Submit your code checker.sv file through Blackboard Learn.
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